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ATmega128
SS Pin
Functionality
Slave Mode
Master Mode
W hen the SPI is configured as a slave, the Slave Select (SS) pin is always input. W hen SS is
held low, the SPI is activated, and MISO becomes an output if configured so by the user. All
other pins are inputs. W hen SS is driven high, all pins are inputs except MISO which can be user
configured as an output, and the SPI is passive, which means that it will not receive incoming
data. Note that the SPI logic will be reset once the SS pin is driven high.
The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous
with the master clock generator. W hen the SS pin is driven high, the SPI slave will immediately
reset the send and receive logic, and drop any partially received data in the Shift Register.
W hen the SPI is configured as a master (MSTR in SPCR is set), the user can determine the
direction of the SS pin.
If SS is configured as an output, the pin is a general output pin which does not affect the SPI
system. Typically, the pin will be driving the SS pin of the SPI slave.
If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin
is driven low by peripheral circuitry when the SPI is configured as a master with the SS pin
defined as an input, the SPI system interprets this as another master selecting the SPI as a
slave and starting to send data to it. To avoid bus contention, the SPI system takes the following
actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a slave. As a result of the
SPI becoming a slave, the MOSI and SCK pins become inputs.
2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is
set, the interrupt routine will be executed.
Thus, when interrupt-driven SPI transmission is used in master mode, and there exists a possi-
bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the
MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI master
mode.
SPI Control Register –
SPCR
Bit
Read/ W rite
Initial Value
7
SPIE
R/ W
0
6
SPE
R/ W
0
5
DORD
R/ W
0
4
MSTR
R/ W
0
3
CPOL
R/ W
0
2
CPHA
R/ W
0
1
SPR1
R/ W
0
0
SPR0
R/ W
0
SPCR
? Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if
the global interrupt enable bit in SREG is set.
? Bit 6 – SPE: SPI Enable
W hen the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI
operations.
? Bit 5 – DORD: Data Order
W hen the DORD bit is written to one, the LSB of the data word is transmitted first.
W hen the DORD bit is written to zero, the MSB of the data word is transmitted first.
? Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic
zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,
166
2467X–AVR–06/11
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